As devices become smaller and integration density increases, high density plasma chemical vapor deposition (HDP-CVD) processes have become a key process due to superior gap-filling capability. In particular, high density plasma (HDP-CVD) processes, using plasma generating power sources such as electron cyclotron resonance (ECR) and inductively coupled plasma (ICP) processes produce high-quality silicon dioxide and silicon nitride layers. Generally, HDP-CVD provides a high density of plasma ions resulting in higher quality films at lower deposition temperatures compared to thermal process. HDP-CVD is particularly ideal for forming PMD oxide layers because of its superior gap filling capability. In an HDP-CVD process, both sputtering and deposition take place simultaneously, resulting in a deposition/sputter ratio (D/S) ratio that may be adjusted according to process parameters.
In prior art HDP-CVD deposition processes, an RF bias power is coupled to the semiconductor wafer by an E-chucking process, where a Voltage is applied to the wafer chuck to create an electrostatic attraction to the process wafer. The RF bias power serves to attract ions which sputter (etch) the wafer during deposition, thereby preventing a phenomenon known as crowning where the deposition material converges over a gap before the gap is completely filled with the deposition material. The deposition process is thereby capable of being tuned by adjusting a D/S ratio to avoid crowning and the creation of voids.
As CMOS device characteristic dimensions shrink to below about 0.1 micron including to about 0.6 microns, the issue of plasma induced damage to CMOS devices becomes a more important factor to consider as smaller CMOS devices have a lower acceptable plasma damage threshold. Prior art HDP-CVD processes may induce an unacceptable level of plasma damage in CMOS devices with characteristic dimensions less than about 0.1 microns.
In addition, the high density of the plasma can result in significant heating of the wafer during deposition requiring a cooled wafer chuck to cool the wafer during deposition. Prior art HDP-CVD deposition processes, including mechanisms for cooling the wafer may be less than adequate as device sizes shrink and devices become more sensitive to higher temperatures, for example including undesired diffusion of dopants in doped regions altering critical boundaries including source/drain extension (SDE) regions and source/drain regions.
For example, higher sputtering rates (lower D/S ratios), which are necessary for good gap-filling tends to increase the temperature of the wafer substrate. Prior art HDP-CVD processes have found it difficult to achieve good gap filling while maintaining the wafer temperature below a desired level. On the other hand, low D/S ratio with high sputtering rates to maintain a desired low temperature results in the creation of voids, thereby compromising device performance and reliability.
There is therefore a need in the semiconductor processing art to develop an improved HDP-CVD process including PMD layer formation whereby a sufficient gap filling ability is maintained while simultaneously reducing plasma damage and maintaining low process wafer deposition temperatures.
It is therefore an object of the invention to provide an improved HDP-CVD process including PMD layer formation whereby a sufficient gap filling ability is maintained while simultaneously reducing plasma damage and maintaining low process wafer deposition temperatures, in addition to overcoming other shortcomings and deficiencies of the prior art.